tm january 2009 fdd8444l_f085 n-channel powertrench ? mosfet ? 2009 fairchild semiconductor corporation fdd8444l_f085 rev a (w) www.fairchildsemi.com 1 fdd8444l_f085 n-channel powertrench ? mosfet 40v, 50a, 6.0 m ? features ? typ r ds(on) = 3.8m ? at v gs = 5v, i d = 50a ? typ q g(tot) = 46nc at v gs = 5v ? low miller charge ? low q rr body diode ? uis capability (single pulse/ repetitive pulse) ? qualified to aec q101 ? rohs compliant applications ? automotive engine control ? powertrain management ? solenoid and motor drivers ? electronic transmission ? distributed power architecture and vrms ? primary switch for 12v and 24v systems l e a d f r e e m t a e l n t i o m p e n i
fdd8444l _ f085 n-channel powertrench ? mosfet fdd8444l_f085 rev a (w) www.fairchildsemi.com 2 mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics symbol parameter ratings units v dss drain to source voltage 40 v v gs gate to source voltage 20 v i d drain current continuous (t c < 150c, v gs = 10v) (note 1) 50 a continuous (t amb = 25 o c, v gs = 10v, with r ja = 52 o c/w) 16 pulsed see figure 4 e as single pulse avalanche energy (note 2) 295 mj p d power dissipation 153 w derate above 25 o c1.02w/ o c t j , t stg operating and storage temperature -55 to +175 o c r jc thermal resistance, junction to case 0.98 o c/w r ja thermal resistance, junction to ambient to-252, 1in 2 copper pad area 52 o c/w package marking and ordering information device marking device package reel size tape width quantity fdd8444l fdd8444l_f085 to-252aa 13? 12mm 2500 units electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 40 - - v i dss zero gate voltage drain current v ds = 32v, - - 1 a v gs = 0v t j = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a11.83v r ds(on) drain to source on resistance i d = 50a, v gs = 10v - 3.5 5.2 m ? i d = 50a, v gs = 5v - 3.8 6.0 i d = 50a, v gs = 4.5v - 4.0 6.5 i d = 50a, v gs = 5v, t j = 175 o c - 6.8 10.7 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 5530 - pf c oss output capacitance - 605 - pf c rss reverse transfer capacitance - 400 - pf r g gate resistance f = 1mhz - 1.7 - ? q g(tot) total gate charge at 5v v gs = 0 to 5v v dd = 20v i d = 50a i g = 1.0ma -4660nc q g(th) threshold gate charge v gs = 0 to 2v - 5.4 7 nc q gs gate to source gate charge - 16.3 - nc q gs2 gate charge threshold to plateau - 10.9 - nc q gd gate to drain ?miller? charge - 21 - nc
fdd8444l _ f085 n-channel powertrench ? mosfet fdd8444l_f085 rev a (w) www.fairchildsemi.com 3 electrical characteristics t j = 25 o c unless otherwise noted switching characteristics drain-source diode characteristics notes: 1: package current limitation is 50a. 2: starting t j = 25 o c, l = 0.37mh, i as = 40a. symbol parameter test conditions min typ max units t on turn-on time v dd = 20v, i d = 50a v gs = 5v, r gs = 2 ? - - 104 ns t d(on) turn-on delay time - 18.7 - ns t r turn-on rise time - 46 - ns t d(off) turn-off delay time - 42 - ns t f turn-off fall time - 19.2 - ns t off turn-off time - - 96 ns v sd source to drain diode voltage i sd = 50a - 0.9 1.25 v i sd = 25a - 0.8 1.0 t rr reverse recovery time i f = 50a, di f /dt = 100a/ s -3444ns q rr reverse recovery charge - 29 38 nc this product has been designed to meet the extreme test conditi ons and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certificat ion.
fdd8444l _ f085 n-channel powertrench ? mosfet fdd8444l_f085 rev a (w) www.fairchildsemi.com 4 typical characteristics figure 1. normalized po wer dissipation vs case temperature 0 25 50 75 100 125 150 175 0.0 0.2 0.4 0.6 0.8 1.0 1.2 power dissipation multiplier t c , case temperature ( o c ) figure 2. 25 50 75 100 125 150 175 0 20 40 60 80 100 120 140 v gs = 5v t c , case temperature ( o c ) i d , drain current (a) v gs = 10v current limited by package maximum continuous drain current vs case temperature figure 3. 10 -5 10 -4 10 -3 10 -2 10 -1 0.01 0.1 1 single pulse d = 0.50 0.20 0.10 0.05 0.02 0.01 normalized thermal impedance, z t jc t, rectangular pulse duration(s) duty cycle - descending order 2 10 0 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c p dm t 1 t 2 normalized maximum transient thermal impedance figure 4. peak current capability 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 100 1000 transconductance may limit current in this region v gs = 10v single pulse i dm , peak current (a) t, rectangular pulse duration(s) 4000 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows:
fdd8444l _ f085 n-channel powertrench ? mosfet fdd8444l_f085 rev a (w) www.fairchildsemi.com 5 figure 5. 1 10 100 0.1 1 10 100 1000 single pulse t j = max rated t c = 25 o c operation in this area may be limited by r ds(on) limited by package 10us 100us 1ms 10ms i d , drain current (a) v ds , drain to source voltage (v) dc forward bias safe operating area 0.01 0.1 1 10 100 1000 1 10 100 starting t j = 150 o c starting t j = 25 o c i as , avalanche current (a) t av , time in avalanche (ms) 500 t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r z 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] note: refer to fairchild application notes an7514 and an7515 figure 6. unclamped inductive switching c apability figure 7. 0.51.01.52.02.53.03.5 0 20 40 60 80 100 t j = -55 o c t j = 25 o c t j = 175 o c pulse duration = 80 p s duty cycle = 0.5% max v dd = 5v i d , drain current (a) v gs , gate to source voltage (v) transfer characteristics figure 8. 012345 0 50 100 150 200 pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) v gs = 10v v gs = 3v v gs = 5v v gs = 4v v gs = 3.5v saturation characteristics figure 9. 345678910 0 5 10 15 20 25 30 t j = 25 o c i d = 50a pulse duration = 80 p s duty cycle = 0.5% max t j = 175 o c r ds(on) , drain to source on-resistance ( m : ) v gs , gate to source voltage ( v ) drain to source on-res i stance variation vs gate to source voltage figure 10. -80 -40 0 40 80 120 160 200 0.6 0.8 1.0 1.2 1.4 1.6 1.8 pulse duration = 80 p s duty cycle = 0.5% max i d = 50a v gs = 10v normalized drain to source on-resistance t j , junction temperature ( o c ) normalized drain to source on resistance vs junction temperature typical characteristics
fdd8444l _ f085 n-channel powertrench ? mosfet fdd8444l_f085 rev a (w) www.fairchildsemi.com 6 figure 11. -80 -40 0 40 80 120 160 200 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v gs = v ds i d = 250 p a normalized gate threshold voltage t j , junction temperature ( o c ) normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature -80 -40 0 40 80 120 160 200 0.90 0.95 1.00 1.05 1.10 i d = 250ua normalized drain to source breakdown voltage t j , junction temperature ( o c ) figure 13. 0.1 1 10 100 1000 10000 f = 1mhz v gs = 0v c rss c oss c iss v ds , drain to source voltage ( v ) capacitance (pf) 60 capacitance vs drain to source voltage figure 14. 0 20406080100 0 2 4 6 8 10 i d = 50a v dd = 25v v dd = 20v v gs , gate to source voltage(v) q g , gate charge(nc) v dd = 15v gate charge vs gate to source voltage typical characteristics
fdd8444l_f085 rev a (w) www.fairchildsemi.com 7 fdd8444l_f085 n-channel powertrench ? mosfet rev. i37 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. * ezswitch? and flashwriter ? are trademarks of system general corporati on, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support d evices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms build it now? 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